Understanding the Various Technological Pathways of Photovoltaic Cells

Understanding Various Technological Routes of Photovoltaic Cells

Since 2022, battery technologies such as TOPCon, HJT, and XBC have initiated a new cycle of expansion, significantly influencing the evolution of the photovoltaic industry. This chapter begins with the working principles of photovoltaic cells, reviewing the technological development history and differences between battery technologies. It clarifies the approaches and paths for improving photovoltaic cell efficiency, laying the groundwork for subsequent cost analysis and trend outlook.

1. Overview of Photovoltaic Cell Technologies

The working principle of photovoltaic cells is based on the photovoltaic effect in semiconductors, first discovered by French scientist Edmont Becquerel in 1839. Under illumination, photons with energy greater than the semiconductor’s bandgap are absorbed, exciting electrons from the valence band across the bandgap to become free electrons in the conduction band, leaving behind holes in the valence band and forming electron-hole pairs. Under the influence of a built-in electric field formed by P-type and N-type semiconductors, electrons and holes move in specific directions, generating electric current.

The bandgap width of semiconductor materials critically determines the short-circuit current and open-circuit voltage of the cells (short-circuit current increases as bandgap width decreases, while open-circuit voltage decreases). Studies suggest that suitable semiconductor materials for photovoltaic cells should have a bandgap width in the range of 1.1-1.6 eV. This has led to the formation of three technological routes: crystalline silicon solar cells, inorganic thin-film solar cells, and new solar cells represented by perovskite materials.

Currently, the global photovoltaic market is predominantly led by more mature crystalline silicon cells. According to CPIA statistics, the market share of crystalline silicon cells was approximately 96.2% in 2021. The bandgap width of silicon materials is 1.12 eV, allowing for about 49% of photon energy to be absorbed at room temperature. Additionally, due to the difference between the bandgap potential and the open-circuit voltage, the effective output of electric energy is approximately 60%. Therefore, the efficiency limit of silicon-based single-junction cells at room temperature is about 29.4%. Theoretically, the optimal bandgap width for semiconductors should be 1.4 eV, leading to a theoretical efficiency limit of 33.7%. Perovskite materials fall within this optimal range, and materials like cadmium telluride also have bandgap widths closer to the optimal value. Consequently, second and third-generation battery technologies are theoretically more efficient than first-generation crystalline silicon cells.

Furthermore, stacking different semiconductor materials to create multi-junction cells can broaden the energy absorption range of photons, further enhancing the theoretical efficiency limit to over 40%. This represents an important development direction for photovoltaic cell technology.

This report focuses primarily on mainstream crystalline silicon cell technology. Although the theoretical efficiency limit of crystalline silicon cells is only 29.4%, due to energy losses in reality, the highest efficiency achieved in laboratory settings is around 26.8%, and the mass production efficiency is about 26%, indicating room for improvement.

Specifically, energy loss can be categorized into optical losses and electrical losses. Optical losses occur because photons cannot be absorbed by the silicon substrate, caused by factors such as surface reflection, long-wave projection, or shading from electrode grid lines. Electrical losses can be divided into recombination losses and ohmic losses (resistive losses). The former refers to the reduction in current due to recombination of electrons and holes before current formation, while the latter refers to losses incurred during current transmission due to resistance.

The focus of photovoltaic cell technology development lies in optimizing cell structures and materials to minimize optical and electrical losses. From the earliest commercialized aluminum back surface field cells (Al-BSF) to the single crystal PERC cells that have driven photovoltaic parity, the primary approach to improving efficiency involves optimizing passivation structures and electrode contact methods to reduce recombination and ohmic losses. Entering the N-type cell era, both TOPCon and HJT cells have adopted “passivated contact” technology to further reduce electrical recombination losses. The BC cell, on the other hand, takes a different path by relocating the front surface electrodes to the back, reducing shading from grid lines and thereby minimizing optical losses. As a platform technology, it can also integrate the advantages of both TOPCon and HJT to form the more efficient XBC cell route.

Looking ahead, breakthroughs in the research of new materials like perovskite not only promise to drive the development of the next generation of solar cells but also enable crystalline silicon cells to combine with new materials to explore breakthroughs towards higher efficiency multi-junction cells.

2. Structure and Efficiency Improvement Strategies of Photovoltaic Cells

1. From BSF to Monocrystalline PERC

The main structure of crystalline silicon cells includes PN junctions, passivation films, and metallized electrodes: the PN junction, comprising negatively charged P-type and positively charged N-type regions, generates an internal electric field that directs the movement of electrons and holes to produce current. The passivation film reduces recombination losses on the silicon wafer surface, while the metal electrode grid collects and conducts the current. Taking PERC cells as an example, phosphorus doping on P-type silicon substrates can create an N-type emitter region, forming a PN junction with the silicon wafer. Aluminum oxide and silicon nitride films are deposited on the back surface to provide passivation and reduce reflection; the positive silver electrode on the front surface, along with the aluminum back field and back silver electrode, constitutes the cell’s metallization structure. Additionally, the inverted pyramid light-trapping structure formed on the front surface and the silicon nitride film serve to minimize surface reflection.

Before the advent of PERC cells, aluminum back surface field cells (Al-BSF) were the first commercially viable crystalline silicon cell structure, first proposed in 1973 and achieving over 90% market share by 2016. BSF cells have several advantages, including simple processing, low cost, and mature technology. However, due to the full-area contact between the aluminum back surface and the silicon substrate, significant surface recombination losses occur, preventing efficiency from exceeding the 20% barrier. PERC (Passivated Emitter and Rear Contact) technology, first proposed in 1989 by a research team led by Martin Green at the University of New South Wales, initially used silicon oxide as the passivation and anti-reflection layer, resulting in a complex and costly technology. It wasn’t until around 2010, when aluminum oxide (Al2O3) was adopted as the passivation interface layer, that PERC cells began to enter the industrialization process.

PERC cells improve upon BSF cells in two main ways: first, by adding a back aluminum oxide layer for passivation, and second, by changing the contact method between the aluminum back surface and the silicon wafer from full-area contact to line contact (LBSF). The passivation mechanisms include field-effect passivation, which creates an electric field at the interface to repel similarly charged carriers and reduce recombination, and chemical passivation, where free hydrogen saturates dangling bonds at lattice defects in the silicon substrate, weakening recombination effects. For P-type silicon wafer surfaces, aluminum oxide is the optimal passivation material: it is negatively charged, generating an effective field passivation effect at the interface, while also providing sufficient hydrogen during preparation to saturate the dangling bonds on the silicon surface, achieving effective chemical passivation.

After adopting aluminum oxide as the passivation layer, PERC cells achieve over 1% higher efficiency compared to BSF cells. In terms of contact methods, direct contact between metal electrodes and silicon wafers leads to significant minority carrier recombination at the contact interface, negatively impacting conversion efficiency. PERC cells change the contact from full-area to line contact, reducing recombination losses by minimizing contact area. On the front surface, PERC cells further employ selective emitter (SE) technology to reduce resistance and recombination losses. SE technology involves creating a gradient of impurity concentration at the contacts between the metal electrodes and the PN junction N-type region, which increases effective carrier collection and reduces resistance. However, high concentration doping can also lead to increased surface recombination losses, so high concentration doping is only performed locally to balance the resistance and recombination loss during metal-semiconductor contact.

The industry gradually completed the overlay of SE technology around 2017, pushing the conversion efficiency of PERC cells to about 23.5%. As the efficiency of PERC technology improved and mass production processes matured, the market share of PERC cells began to rise at a rate of about 20% annually from 2017, surpassing BSF cells by 2019, and reaching approximately 91% market share by 2021. During the same period, photovoltaic cells also experienced competition between monocrystalline and multicrystalline silicon wafer materials. Monocrystalline silicon wafers, with their complete lattice arrangement and fewer internal defects and impurities, exhibit superior electrical performance and conversion efficiency compared to multicrystalline wafers. After the industry gradually overcame issues related to monocrystalline module CTM and light-induced degradation in the second half of 2015, the penetration rate of monocrystalline modules entered a steady upward trajectory. In 2019, the market share of monocrystalline modules first exceeded half, reaching 60%, and further increased to 86.9% in 2020, essentially becoming the market mainstream. Meanwhile, multicrystalline modules began to exit the market, with sales and public quotes virtually ceasing by 2021.

2. From P-Type to N-Type Silicon Wafers

Silicon wafers can be either P-type or N-type depending on the dopant used: P-type wafers primarily incorporate boron or gallium, with minority carriers being electrons, while N-type wafers mainly use phosphorus, with minority carriers being holes. Compared to P-type wafers, solar cells based on N-type wafers have several advantages in performance, including higher minority carrier lifetimes, better impurity tolerance, no light-induced degradation, and lower temperature coefficients. The performance differences between P- and N-type wafers stem from the fact that metal impurities like Fe, Cu, and Ni generally carry positive charges and have a stronger ability to capture electrons. Since the minority carriers are electrons in P-type wafers and holes in N-type wafers, P-type wafers are less resistant to contamination. Under identical metal impurities, N-type wafers demonstrate significantly higher minority carrier lifetimes (research indicates that N-type wafers of the same resistivity have minority carrier lifetimes 1-2 orders of magnitude higher than P-type). The higher the minority carrier lifetime, the higher the photoelectric conversion efficiency, making N-type wafers inherently more efficient.

Additionally, boron in the silicon wafer can form boron-oxygen complexes when exposed to light or current injection, which capture the generated carriers and reduce minority carrier lifetime, causing light-induced degradation (LID). The industry’s main approach to mitigating light degradation in P-type wafers is to lower the boron or oxygen content, typically achieved through high-purity crucibles during monocrystalline growth or co-doping with boron-gallium to reduce boron content. However, the former increases wafer costs, while the latter reduces cell efficiency. Conversely, N-type wafers, with their low boron content, inherently minimize the occurrence of light-induced degradation.

In the past, N-type wafer development was limited due to immature technology and high costs. However, with the advancement of next-generation battery technologies like TOPCon and HJT, as well as ongoing improvements in wafer processing techniques, the market share of N-type wafers is expected to continue rising, gradually replacing P-type wafers.

3. N-Type Battery Technologies: TOPCon and HJT

(1) TOPCon Cells

TOPCon (Tunnel Oxide Passivated Contact) technology was first proposed by the Fraunhofer Institute at the 28th European PVSEC in 2013, achieving a laboratory efficiency record of 25.8% on 4 cm² cells in 2017. According to a theoretical model established by Jan Schmidt and others in 2018, the theoretical efficiency limit of TOPCon cells can reach 28.7%. The main feature of TOPCon cells is the use of a tunneling oxide layer combined with a doped polysilicon layer in the passivated contact technology. This passivated contact involves using a very thin dielectric film to isolate the metal electrode from the semiconductor, allowing carrier tunneling while effectively reducing recombination losses caused by direct contact between the metal electrode and the silicon wafer, thus achieving both passivation and contact effects.

In the passivated contact structure of TOPCon cells, the silicon oxide layer (SiO2) primarily serves the roles of passivation and tunneling, while the doped polysilicon layer (poly-Si) can form a high-low junction structure with the N-type silicon substrate, reducing recombination losses at the silicon interface while providing good conductivity for carriers. Furthermore, the main differences between TOPCon and PERC cells include: (1) the formation method of the PN junction changes from phosphorus doping in PERC cells to boron doping in TOPCon cells; (2) due to lower boron doping concentrations, the resistance in the front surface emitter region is higher, necessitating the use of silver-aluminum paste to create the metal fine grid on the front surface, allowing aluminum atoms to enter the emitter region during the sintering process and form a P+ region, creating a high-low junction with the silicon’s P-type region to reduce resistance; (3) the back passivated contact structure of TOPCon resolves the issue of carrier conduction, allowing the metal electrode to avoid contact with the silicon substrate, thus eliminating the need for aluminum back field preparation and laser grooving; (4) TOPCon cells have retained the passivation film and anti-reflection layer structure (aluminum oxide + silicon nitride) from PERC cells, but this structure has been moved to the front surface.

Currently, mass-produced TOPCon cells only apply the passivated contact structure to the back surface, while the front surface still uses the PERC cell structure (aluminum oxide + silicon nitride) for passivation, resulting in some efficiency loss. In fact, to achieve the theoretical efficiency limit of 28.7% for TOPCon cells, a bifacial passivated contact structure is necessary. The theoretical limit efficiency for cells with only back passivated contact structure is approximately 27.1%. The highest laboratory efficiency record for TOPCon cells achieved by domestic manufacturers is held by Zhonglai Co., which attained a conversion efficiency of 26.7% on M10-sized N-type cells in April of this year, breaking the previous record of 26.4% set by JinkoSolar in December 2022. Other leading domestic manufacturers that have delved into TOPCon technology research include Trina Solar, Canadian Solar, and Longi Green Energy.

(2) HJT Cells

HJT (Heterojunction with Intrinsic Thin Film) technology was first proposed by Sanyo Electric’s research department in the late 1980s and patented under the HIT trademark in 1991. After the patent expired in 2011, manufacturers began laboratory research and scaling up production of heterojunction cells. In 2021, Longi’s Wei Long and others estimated the theoretical efficiency of HJT cells to be 28.5%, providing an efficiency advantage over single-sided passivated contact TOPCon cells. Both PERC and TOPCon cells form PN junctions directly on silicon substrates (c-Si) through doping, meaning both P-type and N-type regions are formed within the same semiconductor, referred to as homojunctions. In contrast, HJT cells’ PN junction is composed of an N-type silicon wafer substrate (c-Si) and a doped amorphous silicon thin film (a-Si), making it a heterojunction cell.

Structurally, HJT cells use N-type silicon wafers as substrates, depositing intrinsic hydrogenated amorphous silicon (a-Si:H) thin films on both the front and back surfaces as passivation structures. On the front surface, a P-type doped hydrogenated amorphous silicon layer is deposited, forming a PN junction with the silicon wafer substrate, while an N-type doped hydrogenated amorphous silicon layer is deposited on the back surface, forming a high-low junction (N+/N) structure with the silicon wafer substrate. Due to the high contact resistance of hydrogenated amorphous silicon, a transparent conductive oxide (TCO) layer is required to facilitate carrier transmission and reduce reflection. Finally, the metallization process for HJT cells employs low-temperature silver paste, as the hydrogenated amorphous silicon requires a strict temperature constraint (below 200°C). This necessitates a shift from high-temperature silver paste used in PERC and TOPCon cells.

The highest laboratory efficiency record for HJT cells from domestic manufacturers is held by Longi Green Energy, which achieved a conversion efficiency of 26.81% in November 2022 with its microcrystal technology HJT cells, breaking the previous record of 26.41% set by Maike Co. and Sundrive in September 2022. Other leading domestic manufacturers with HJT technology reserves include Tongwei Co., Canadian Solar, JA Solar, and Trina Solar, with companies like Daqo New Energy, Huasheng New Energy, Aiko Technology, and Hanergy making significant investments in the HJT cell route.

4. Platform Technologies: XBC Cells

IBC (Interdigitated Back Contact) cells were first proposed by Schwartz and Lammert in 1975. The most distinctive feature of IBC cells is the arrangement of all metal electrodes originally distributed on the front and back surfaces in a finger-like pattern on the back surface. Consequently, the PN junction’s P-type region and N-type high-low junction also move to the back surface and are arranged in a finger-like pattern. This design aims to avoid shading from the front surface electrode grid lines, maximizing the utilization of incident light and reducing optical losses. Additionally, since shading is no longer a concern, the metal grid lines can be made wider, reducing resistance, and the doping concentration of the PN junction can be minimized to reduce recombination losses. To ensure that photogenerated carriers are minimally recombined before reaching the back PN junction, BC cells generally require higher minority carrier lifetimes, often using N-type silicon wafers to guarantee higher carrier collection rates.

Classic IBC cells use N-type silicon wafers as substrates, doping the front surface to form N+/N front surface fields (FSF) to reduce surface recombination losses. The back surface is formed by phosphorus and boron doping to create finger-like arranged P+ emitters and N+ back fields (BSF), where the P+ emitter forms a PN junction with the silicon wafer substrate, and the N+ back field forms an N+/N high-low junction. Both front and back surfaces use silicon oxide and silicon nitride stacked films as passivation layers. The width of the P+ emitter and N+ back field, along with the spacing between them, significantly influences cell performance. Generally, both the N+ back field and the spacing should be minimized, increasing the complexity of the manufacturing process.

Since IBC cells adopt a fundamentally different efficiency improvement approach compared to TOPCon, HJT, and others, they can leverage their advantages while being compatible with other battery technologies, also known as BC cells or XBC cells. Theoretically, the BC structure can enhance cell conversion efficiency by 0.6-0.7%, making it a high-potential platform technology that is likely to become the next mainstream technology route. Specifically: (1) the combination with TOPCon forms TBC cells: using N-type silicon wafers as substrates, the front surface forms an N+ front surface field through phosphorus doping, depositing aluminum oxide + silicon nitride as passivation and anti-reflection layers; the back surface deposits a tunneling oxide layer, creating spaced P-type doped polysilicon and N-type doped polysilicon layers, finally depositing a silicon nitride passivation layer and opening contacts to the P+ and N+ regions for positive and negative electrodes; Longi has developed HPBC cells based on P-type silicon wafers, incorporating features from IBC, PERC, and TOPCon, primarily differing in using boron doping on the front surface instead of phosphorus. (2) the combination with HJT forms HBC cells: using N-type silicon wafers as substrates, depositing hydrogenated amorphous silicon thin films as passivation layers on the front surface, replacing the transparent conductive film with a silicon nitride anti-reflection layer; depositing hydrogenated amorphous silicon thin films as passivation layers on the back surface, creating spaced P-type and N-type doped amorphous silicon layers, and finally depositing a transparent conductive film and opening contacts to the P+ and N+ regions for positive and negative electrodes.

SunPower is a leader and pioneer in IBC cells, having launched its third-generation IBC cells in 2015, achieving a mass production efficiency of 25%. The planned seventh-generation product from its spinoff Maxeon is expected to combine the passivated contact structure of TOPCon cells, with an estimated mass production efficiency exceeding 26%, leading the mainstream PERC technologies by 2-3 percentage points, and being about 1 percentage point higher than TOPCon and HJT N-type battery technologies. Currently, the highest laboratory efficiency record for BC cells was achieved by Kaneka in Japan in 2017, utilizing the HBC route with an efficiency of 26.7%. On the domestic front, Longi Green Energy and Aiko Technology have achieved mass production, with Longi’s HPBC products reaching a mass production efficiency of 25.3% and Aiko’s ABC products (route not disclosed) reaching 26.5% efficiency. Apart from their efficiency advantages, BC cells, with their completely unobstructed front surface, appear more aesthetically pleasing. If the battery frame is also changed to black materials, a fully black component product can be achieved.

2. Production Process and Cost Analysis of Photovoltaic Cells

Despite the continuous iteration of technological routes in photovoltaic cells, the fundamental principles, core structures, and key processes based on crystalline silicon cells remain unchanged. As different routes emerge with variations in material selection and structural arrangement, the processes and equipment for cell preparation are continually evolving. Battery manufacturers and equipment manufacturers aim to enhance yield and reduce costs through continuous optimization of production line designs. This chapter first clarifies the core processes of photovoltaic cell production (cleaning and texturing, diffusion, film deposition, and metallization) and mainstream process equipment, then systematically outlines the main process steps and production costs for TOPCon, HJT, and XBC cells, establishing a comparative framework for the costs of different battery technologies and trend assessments to inform future analyses of battery manufacturers’ mass production strategies and profitability.

1. Core Processes and Technical Route Differences

1. Cleaning and Texturing

Cleaning and texturing is the first process in all battery preparation routes. Cleaning removes oils, metal contaminants, and mechanical damage from the silicon wafer’s surface using alkaline solutions, minimizing impurities’ impact on cell yield. Texturing involves etching specific crystal-oriented single-crystal silicon wafers in alkaline solutions to create a rough inverted pyramid structure on the surface, increasing the silicon wafer’s surface area and reducing reflection losses. Currently, the mainstream process is a wet process, utilizing solutions, acids, alkalis, surfactants, and other methods to chemically react with and dissolve impurities on the silicon wafer’s surface. Cleaning equipment primarily consists of single-wafer cleaning and tank cleaning systems. For PERC and TOPCon cell routes, there are no significant differences in the cleaning and texturing stages; however, HJT cells require new cleaning equipment due to their low-temperature production processes. Global semiconductor cleaning equipment is heavily concentrated in Japanese companies, while domestic manufacturers have made significant progress towards localization, with leading equipment suppliers including Jiejia Weichuang and Beifang Huachuang.

2. Diffusion

Diffusion refers to the process of forming PN junctions and high-low junctions through high-temperature chemical diffusion principles. The essence of the reaction involves doping P-type or N-type silicon wafers with impurity elements, allowing these impurities to penetrate the silicon substrate’s lattice structure to form higher concentrations of holes or electrons, generating an internal electric field due to the concentration difference. P-type silicon wafers inherently have high hole concentrations, using phosphorus doping during the junction formation process, while N-type wafers utilize boron doping. The diffusion processes for PERC and TOPCon cells primarily employ thermal diffusion methods using low-pressure tube diffusion furnaces. In contrast, HJT cells embed the doping process within the thin film deposition process described in the next section, mainly utilizing ion implantation or vapor deposition methods. By the time the PERC battery route matured, domestic phosphorus diffusion equipment had achieved full localization and introduced models suitable for large silicon wafers and high production capacities. To address issues with thermal and gas uniformity, the doping process has evolved into various placement modes, including horizontal, vertical, and PE-type vertical arrangements. Boron diffusion presents greater challenges than phosphorus diffusion, thus requiring higher equipment standards for the TOPCon route, manifested in greater uniformity demands, higher diffusion temperatures (typically above 1000°C), and longer diffusion times (film formation times typically need to reach 240 minutes), consequently increasing production costs for TOPCon cells during diffusion. The doping principle is thermal diffusion; besides low-pressure tube diffusion furnaces, laser equipment can be used for localized heating, mainly applied in selective emitter (SE) preparations. Lasers enable precise heating, allowing boron or phosphorus atoms formed in boron-silicon glass (BSG) or phosphorus-silicon glass (PSG) on the silicon wafer surface to diffuse into the silicon substrate, creating localized high-concentration doping. Given the technical difficulty of boron diffusion, SE on boron diffusion presents greater challenges than on phosphorus diffusion. Leading equipment companies have successfully developed and piloted these techniques, while some manufacturers are currently validating them with clients. Lastly, the phosphorus or boron-silicon glass layers on the silicon wafer’s surface adversely affect subsequent processes and may lead to PN junction leakage, necessitating chemical etching and cleaning after doping is completed.

3. Film Deposition

Film deposition refers to the preparation of various thin films in the battery structure, such as aluminum oxide and silicon nitride films in PERC cells, tunneling oxide and doped polysilicon layers in TOPCon cells, and hydrogenated amorphous silicon layers and transparent conductive layers in HJT cells. This is a core step in photovoltaic cell preparation. Film deposition processes primarily occur in vacuum environments and can be broadly categorized into physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). PVD involves vaporizing material sources directly into atomic, molecular, or ionic states and depositing them on the substrate surface through low-pressure processes. CVD generates deposits on the substrate surface through chemical reactions. ALD involves depositing materials one atomic layer at a time on the substrate surface.

Different thin film layers possess distinct characteristics and deposition principles that are suitable for various process routes. Currently, the aluminum passivation structure on the back of PERC cells and the front of TOPCon cells primarily use ALD, PECVD (plasma-enhanced chemical deposition), and other processes. The tunneling oxide layer in TOPCon cells can be made using LPCVD (low-pressure chemical deposition), PECVD, or ALD processes. The doped polysilicon layer is produced through LPCVD or PECVD processes. HJT cells use PECVD or CAT-CVD (hot wire deposition) for the amorphous silicon layers, while the transparent conductive layer is made through PVD (sputtering) or RPD (evaporation). In the design of battery production lines, it is essential to consider the preparation processes of different membrane layers, balancing factors such as film quality, film efficiency, equipment investment, and line adaptability to select the most cost-effective process route.

(1) PERC and TOPCon Front Surface – Aluminum Film Deposition

The quality of aluminum film deposition on the front surface of PERC and TOPCon cells is mainly influenced by film density, uniformity, and thickness. According to relevant studies, the optimal thickness for aluminum oxide films is around 3-5 nm for the best passivation effect. Therefore, starting from the quality of aluminum oxide films, the ALD process is superior, while PECVD typically requires a thickness greater than 15 nm for aluminum oxide films. However, PECVD can deposit both aluminum and silicon nitride films in the same equipment, offering better process integration. According to CPIA statistics, in 2021, ALD deposition technology accounted for approximately 41.4% of passivation in PERC cells. It is expected that the market share of the ALD route in the front passivation of TOPCon cells will gradually increase.

(2) TOPCon Cells – Tunneling Oxide Layer and Doped Polysilicon Films

The core difference between TOPCon and PERC cells lies in the passivated contact structure, requiring the addition of tunneling oxide and doped polysilicon layer preparation in the film deposition step. Current mainstream routes include LPCVD and PECVD, with some manufacturers exploring niche routes like PEALD and POPAID. For the preparation of the doped polysilicon layer, both deposition and doping need to be accomplished. The polysilicon layer is typically deposited using LPCVD or PECVD processes, with film thickness generally ranging from 100-150 nm. During the annealing process, the amorphous silicon film changes its crystallinity from a mixed phase of microcrystalline and amorphous to polycrystalline, activating the passivation properties of the film. In terms of doping, the LPCVD and PECVD routes have developed two methods: non-in-situ doping and in-situ doping. The LPCVD route has a slower film formation rate; thus, non-in-situ doping is typically used, where intrinsic polysilicon is first deposited, followed by doping using a diffusion furnace or ion implantation. In contrast, the PECVD route is more efficient, allowing in-situ doping during deposition.

When it comes to the preparation of the tunneling oxide layer, the methods compatible with LPCVD primarily include thermal oxidation, while PECVD-compatible methods include PECVD, PEALD, and thermal oxidation. From the perspective of the density of the silicon oxide membranes produced by different processes, the PEALD route offers the best passivation effect but at a higher equipment cost. Although thermal oxidation and PECVD produce less effective films, they are more economical. Generally, the thickness of ALD films is about 0.7 nm, and thermal oxidation films are around 1.3 nm; the tunneling mechanism for the silicon oxide layer can be achieved when the thickness is below 1.6 nm. Comparatively, the LPCVD route has higher maturity, with extensive industrial application experience. Its advantages include easy control and higher film quality (good uniformity and density). The downside is that the production process may leave a layer of doped polysilicon on the edges of the battery’s front surface, known as “around deposition,” which negatively affects the electrical and optical performance of the battery. Therefore, chemical cleaning is necessary after depositing the polysilicon film, and the deposition rate is relatively slower.

(3) HJT – Hydrogenated Amorphous Silicon and TCO Films

HJT cells require the deposition of 5-10 nm of intrinsic hydrogenated amorphous silicon on both sides of the silicon wafer as a passivation film, along with a 10 nm thick boron-doped P-type amorphous silicon layer on the back side and a 10 nm thick phosphorus-doped N-type amorphous silicon layer on the front side. The mainstream preparation processes for these films include PECVD and CAT-CVD (hot wire deposition) routes. PECVD can be further divided into radio frequency routes (RFCVD, 13.56 MHz) and very high frequency routes (VHFCVD, 30-300 MHz). Compared to other processes, RFCVD has the highest maturity and good film uniformity; VHFCVD has a high deposition rate but moderate film uniformity, with hydrogen content higher than that of radio frequency PECVD; CAT-CVD has a fast deposition rate and the highest hydrogen content but currently faces disadvantages in terms of film uniformity and cost.

From the perspective of efficiency improvement, the passivation structure of HJT cells is nearly perfect. However, the amorphous silicon layers have a narrower optical bandgap, leading to lower optical utilization and affecting the efficiency of the cells. Therefore, the industry is currently upgrading to microcrystalline silicon as a replacement for amorphous silicon. Compared to amorphous silicon, microcrystalline silicon has a wider and continuously adjustable optical bandgap, capturing a broader spectrum of light, while the presence of crystalline silicon grains enhances conductivity, thereby improving conversion efficiency from both optical and electrical perspectives. In the aforementioned preparation processes, VHFCVD and CAT-CVD are more likely to facilitate the introduction of microcrystalline solutions.

The TCO layer mainly consists of a composite of indium, antimony, zinc, tin, cadmium, and their oxides. The preparation processes include PVD and RPD routes, with the former using ITO (indium tin oxide) as the deposition material (known as “target material”) and completing the film through magnetic sputtering methods, which is currently a more mature process for mass production. The latter uses IWO (indium oxide doped with tungsten) as the deposition material and employs ion reaction methods for film deposition. This route reduces the bombardment on the amorphous silicon thin film, thus enhancing battery efficiency and possessing greater industrial potential.

The target material indium is a rare metal, priced around 2000 yuan per kilogram. With the anticipated expansion of HJT production capacity, the price of indium metal and target materials may rise, increasing the cost burden of HJT batteries. Therefore, exploring strategies to reduce indium dependency is a crucial and necessary cost reduction path for HJT battery industrialization. According to the “Three Steps to Reduce Indium” plan announced by leading HJT equipment manufacturer Maike, indium reduction can be achieved through improvements in equipment, film processes, and resource recycling:

1. Enhancing deposition accuracy on the equipment side; the latest equipment has reduced indium target consumption from nearly 20 mg/W to 13.5 mg/W;
2. In film processes, adopting an ITO + AZO (aluminum-doped zinc oxide) layered scheme can further lower target consumption to 6 mg/W;
3. Resource recycling is anticipated to bring GW-level HJT battery factories’ target consumption down to around 1 mg/W.

4. Metallization

The metallization process involves solidifying metal paste into specific shapes on the front and back surfaces of the battery to enable current transmission. As TOPCon and HJT routes employ passivated contact structures, the metallization structure eliminates the aluminum back field used in PERC cells, requiring only the preparation of main and fine grid electrodes. The differences in metallization processes primarily reflect choices in paste selection, grid arrangement, and preparation processes. In terms of paste selection, PERC cells primarily use high-temperature silver paste for electrode grid lines, which includes silver powder and glass powder. During preparation, glass powder melts, etching the silicon wafer’s silicon nitride layer while ensuring silver powder is well arranged, forming silver grid lines after sintering.

The preparation of the back electrode for TOPCon cells is similar to PERC but requires changing the front fine grid paste to silver-aluminum paste to reduce resistance losses, as aluminum elements will deposit at the contact points with the P-type region, forming a P+/P high-low junction. Before the introduction of SE technology in TOPCon cells, this approach effectively reduced resistance losses and improved carrier collection. For HJT cells, due to the low-temperature process, the paste selection must shift from high-temperature silver paste to low-temperature silver paste. Low-temperature silver paste does not contain glass powder but relies on organic resin for binding silver particles. However, the residual organic components increase the electrode’s resistivity, necessitating smaller particle diameters and higher quantities of silver paste (the consumption of silver paste is about twice that of PERC cells), widening the cost gap with PERC and TOPCon cells.

In this context, the industry is developing silver-coated copper paste as a transitional cost-reduction strategy for HJT cells. Silver-coated copper is a core-shell structured material that combines the physical properties of copper with the excellent metallic characteristics of silver (the conductivity of pure copper and pure silver is at the same order of magnitude). The mainstream process currently yields silver content in silver-coated copper powders of around 50%-70%, with long-term goals potentially reducing it to below 30%, thus achieving cost reduction. According to data from Suzhou Jingyin, silver-coated copper maintains similar viscosity, curing temperature, and tensile strength to pure silver paste, with only a slight increase in resistivity. Currently, using silver-coated copper for back fine grids can achieve efficiency parity with pure silver paste, but using silver-coated copper for both front and back fine grids may still result in a 0.1% efficiency loss due to coating issues. Moreover, copper oxidizes easily at high temperatures, making this cost-reduction route suitable only for low-temperature processes like those used in HJT cells.

In terms of grid line arrangement,